Chip Interfaces

16X Data Rate
16X Data Rate is a technology that transfers 16 bits of data per clock cycle, 8 times as many data bits as DDR (Double Data Rate) techniques used in many DRAMs today and twice the bit transfer rate of XDR memory. This technology allows the XDR2 memory system to run at data rates as high as 12.8Gbps at relatively low and economical system clock speeds.
32X Data Rate
Transfers 32 bits of data per I/O on each clock cycle - 16 times as many data bits as the DDR (double data rate) techniques common in many DRAM products today. 32X Data Rate was developed through the Rambus Terabyte Bandwidth Initiative.
Asymmetric Equalization
Enables very high bandwidths on next generation memory systems. Signal equalization is applied asymmetrically across the memory controller - DRAM communication link and improves overall signal integrity while minimizing the complexity and cost of the DRAM device. Asymmetric Equalization was developed through the Rambus Terabyte Bandwidth Initiative.
Auto Precharge
Increases efficiency of memory operations by eliminating the need to send precharge commands.
Enhanced FlexPhase™ Timing Adjustments
Enables flexible phase relationships between signals, allowing precise on-chip alignment of data with clock. FlexPhase enhancements improve the sensitivity and capability of FlexPhase for very high performance memory systems operating at data rates of 10 Gbits and higher. Enhanced FlexPhase was developed through the Rambus Terabyte Bandwidth Initiative.
FlexLink™ C/A Interface
Industry's first full-speed, scalable point-to-point command/address channel. FlexLink C/A provides the command and address information to a DRAM using a single, differential high speed communications channel. FlexLink C/A was developed through the Rambus Terabyte Bandwidth Initiative.
FlexPhase™ Timing Adjustments
Enables flexible phase relationships between signals, allowing precise on-chip alignment of data with clock. FlexPhase technology is a key technology ingredient for achieving high data rates on chip to chip systems that reference an external clock signal. In addition, FlexPhase timing adjustments, which can be particularly beneficial in Fly-by architecture, eliminate many timing offsets associated with process variations, driver/receiver mismatch, on-chip clock skew and clock standing wave effects. FlexPhase technology's automatic centering of data and clock offers designers a quick and easy design solution for high speed chip interconnections.
Fly-by Command and Address
Fly-by command/address architectures improve signal integrity in memory systems, thus enabling higher per-pin bit rates and systems capable of GHz data rates. When used in combination with FlexPhase™ circuits that deskew the timing of source synchronous signals, the Fly-by command/address architecture increases memory bandwidth, maintains low latency, and avoids the need for clock-encoding. Fly-by architectures have been used in Rambus memory systems to enable scalability without compromising data rates.
Fully Differential Memory Architecture (FDMA)
Industry's first memory architecture that incorporates differential signaling technology on all key signal connections between the memory controller and the DRAM. FDMA enables higher speed, lower noise and lower power in high performance memory systems. FDMA was developed through the Rambus Terabyte Bandwidth Initiative.
Fully Synchronous DRAM
Allows precise timing from a DRAM system, improves memory transfer efficiency, and facilitates system pipelining.
In-System IO Margin and Characterization
Improves system reliability and system yields by measuring signal integrity parameters used for speed binning. Improves channel margins and testability by using in-system voltage and timing margin testing for channel diagnostics.
Jitter Reduction Technology
Improves the signal integrity of very high speed communications links. By reducing jitter, memory signaling performance of 16Gbps can be achieved, enabling the terabyte bandwidth performance levels of next generation memory systems. Jitter Reduction Technology was developed through the Rambus Terabyte Bandwidth InitiativeTerabyte Bandwidth Initiative.
Late Write/Write Latency
Improves throughput of a memory device by reducing write-to-read turnaround within the memory core.
Low-Capacitance ESD
Reduces capacitance to enable higher-frequencies of operation while maintaining robust electrostatic discharge (ESD) protection.
Low-Power Initiative For Multi-Gbps Platforms
Low-power techniques for high performance multi-Gbps serial links
Micro-threading
Reduce row and column access granularity resulting in a significant performance benefit for applications dealing with small data objects.
Module Connector Compensation
Improves operating frequency of systems utilizing module connectors by mitigating the impedance discontinuity of the electrical interconnection.